The present invention relates to a semiconductor random access memory cell.
The classic one-transistor dynamic RAM cell, around which memory development has been centered from the 1K bit level up to the 256K bit level, has barriers to scalability which prevent scaling this technology beyond approximately the 1 megabit level. In particular, the specific capacitance of bit lines per unit length ceases to decrease with decreasing bit line geometries, due to fringing field effects. Thus, the quantity of charge stored in a single-transistor memory cell cannot be scaled further, without encountering disastrous effects of vulnerability to alpha-particle induced error and slow read speed.
To avoid this barrier to scaling, various attempts have been made to provide a memory cell which has high density and also has gain in each memory cell. It is also highly desirable that such a memory cell should have reasonably long storage times and reasonable process simplicity.
Thus, it is an object of the present invention to provide a random access memory cell having high density, reasonably long refresh times, and simple fabrication process requirements.
The present invention meets these objectives. The present invention teaches a memory cell which requires only double poly, and requires no metal in the cell itself. (Thus, the designer can use a metal level for, e.g., array architectural features such as segmented bit lines.) Thus, the present invention provides a highly planar memory cell which can be very simply fabricated.
The present invention uses an EPROM-like memory transistor, having source, drain, and channel on the substrate. This transistor is controlled by two gates: a quasi-floating gate composed of thin polysilcon, and a control gate in a second polysilicon layer. The quasi-floating gate is selectively isolated by a polysilicon-channel write transistor. This write transistor comprises a more lightly doped portion of the same polysilicon level which also constitutes the quasi-floating gate. A word line provides both the control gate for the memory transistor and the gate for the polysilicon-channel write transistor.
Thus, in the present invention, the read cycle is a destructive read, so that a write after read (as in the standard DRAM technology) is always necessary. However, because the gain of the memory transistor is greater than the gain of the write transistor, a good read with gain is provided nevertheless.
It should also be noted that the memory cell of the present invention is not exposed to alpha particle induced upset as are most memory cells. Since the store charge which constitutes the signal is stored in an isolated polysilicon layer, carriers generated in the substrate cannot be swept into the stored charge region. Moreover, since the read operation has high gain, a large read signal is provided from a small stored charge. Thus the storage area can have minimum lithographic dimensions, and the cell scales to extremely small dimensions conveniently.
According to the present invention there is provided:
A memory cell comprising:
a semiconductor substrate;
a read bit line in said substrate having a second conductivity type;
a drain voltage line in said substrate having a second conductivity type;
a memory transistor channel region at the surface of said substrate, separating said read bit line from said drain voltage line;
a word line defining a gate above and capacitatively coupled to said memory transistor channel region; and
a thin polysilicon layer, said thin polysilicon layer comprising a quasi-floating gate portion thereof interposed between said word line and said channel region of said memory transistor and capacitatively coupled both to said word line and said channel region of said memory transistor, and said thin polysilicon layer also comprising a polysilicon channel region, said thin polysilicon channel region comprising a dopant concentration which is less than 10.sup.19 per cubic cm, said thin polysilicon channel region being capacitatively coupled to said word line, and said thin polysilicon layer also comprising a heavily doped write bit line portion, said polysilicon channel portion of said thin polysilicon layer being interposed between said write bit line portion and said quasi-floating gate portions respectively of said thin polysilicon layer, said quasi-floating gate having said second conductivity type.